ECE 385 - Digital Systems Laboratory
FPGA-based hardware design and computer architecture.
Motion-Detect Multiplayer Flappy Bird
◦ Architecture: Duo-FPGA system using PMOD interfaces to decouple the real-time computer vision processing from the primary arcade game engine.
◦ Hardware CV Pipeline: Real-time 640x480 video ingest from an OV7670 camera sensor, downsampled to 3-bit grayscale, buffered via BRAM, and filtered using a 3x3 Sobel operator for spatial edge detection.
◦ Motion Tracking: Custom shift-subtract hardware dividers calculating intensity-weighted centroids to track physical motion and transmit physical jump triggers over PMOD.
◦ Game Engine & Rendering: Custom multi-instance physics engine supporting up to 4 concurrent players, featuring custom sprite rendering layers mapped to look-up tables over HDMI.
◦ Skills & Tech: Duo-AMD Urbana FPGAs, SystemVerilog, Vivado RTL, MicroBlaze (HID peripheral interfacing), Sobel Filtering, Image Processing Pipelines.
Edge Detect
Game Play
Set Up
Digital Design Projects
◦ Physical I/O: Keyboard + HDMI Ball Game.
◦ Architecture: SLC-3 (Small Little Computer) Instruction Set Architecture.
◦ Arithmetic: Full, look-ahead, and select adders; hardware multiplier.
◦ Skills: FPGA, SystemVerilog, HDL, Vitis.
Multiplier on FPGA
SLC3 Data Path
